1. Field of the Invention
The present invention generally relates to complimentary metal oxide semiconductor (CMOS) transistor devices, and in particular, the present invention relates to a device structure and method which facilitate the retrofitting of standard CMOS design layouts into back-biased CMOS transistor configurations. Although not limited thereto, the present invention is especially applicable to low-voltage CMOS (LVCMOS), or ultra-low power CMOS(ULP), implementations.
2. Description of the Related Art
FIG. 1(a) illustrates a standard CMOS inverter design having an NFET 101 and a PFET 102, each of which essentially constitutes a three-terminal device. Basic component parts of the NFET 101 include an n-region source 103, a gate electrode 104, an n-region drain 105, and a pxe2x88x92 bulk substrate 106. Typically, the layer 106 is a pxe2x88x92 epitaxial layer grown on a p+ substrate 100. The NFET 101 may be formed in a p-well 107 as shown. The PFET 102 includes p-region source 108, a gate electrode 109, a p-region drain 110, and an n-well 111. In addition, reference numeral 112 denotes a p+ plug which forms a bulk terminal or well tie for the bulk material 106, and reference numeral 113 is representative of an n+ plug forming a well tie for the n-well 111.
In the exemplary CMOS design of FIG. 1(a), the well contact 112 of the bulk material 106 is shorted to the grounded source terminal 103 of the NFET 101 by way of a metallic rail contact 114. Likewise, the well contact 113 of the n-well 111 is shorted to the source terminal 108, connected to a source voltage Vdd, by way of a metallic rail contact 115. Thus, in this example, the substrate bias of the NFET 101 is fixed at GND, and that of the PFET 102 is fixed at Vdd.
FIG. 1(b) illustrates a similar design, except that the substrate or bulk of the NFET 101 is biased to ground by way of a metallic back plane 116, rather than by way of the well tie 112 shown in FIG. 1(a).
It is noted that in the three terminal inverter design of FIGS. 1(a) and 1(b), a source of the NFET is tied to ground and the same of the PFET is tied to Vdd. While the source is tied to ground or Vdd in the case of inverters, such is not the case for compound gate structures with transistors in series, or pass transistor logic. In these topologies, some of the devices may be four terminal devices having different source and bulk potentials.
There are a number of factors which contribute to the magnitude of a transistor device""s threshold voltage. For example, to set a device""s threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a devices""s threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations (such as oxide thickness, and channel width and especially channel length), charge trapping in materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations. This can be accomplished using back biasing, i.e. controlling the potential between a device""s well and source. See James B. Burr, xe2x80x9cStanford Ultra Low Power CMOS,xe2x80x9d Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated herein by reference for all purposes.
A basic characteristic of back-biased transistors resides in the ability to electrically tune the transistor thresholds. This is achieved by reverse biasing the bulk of each MOS transistor relative to the source to adjust the threshold potentials. Typically, the potential will be controlled through isolated ohmic contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions. Exemplary of this is the structure of FIG. 2(a), which illustrates a configuration in which the well contacts are split off from the source contacts.
That is, in the exemplary CMOS configuration of FIG. 2(a), each of an NFET 201 and a PFET 202 essentially constitutes a four-terminal device. As in FIG. 1, the NFET 201 is made up of an n-region source 203, a gate electrode 204, an n-region drain 205, and a pxe2x88x92 bulk substrate 206. Again, the NFET 201 may also include a p-well 207 as shown. Similarly, the PFET 202 includes p-region source 208, a gate electrode 209 and a p-region drain 210 formed in an n-well 211. Reference numeral 212 is a p+ plug which forms a bulk terminal or well tie for the bulk material 206, and reference numeral 213 is an n+ plug forming a well tie for the n-well 211.
In the back-biased CMOS design of FIG. 2(a), the well contact 212 of the bulk material 206 is split off from the source terminal 203 of the NFET 201 by providing a separate metallic rail contact 216 which is spaced from the metallic rail contact 214 of the source terminal 203. Rail contact 216 is connected to a bias voltage source Vpw. Likewise, the well contact 213 of the n-well 211 is split off from the source terminal 208 of the PFET 202 by providing a separate metallic rail contact 218 which is spaced from the metallic rail contact 215 of the source terminal 208. Rail contact 218 is connected to a bias voltage source Vnw. Thus, in this example, the substrate bias potential of the NFET 201 is set by Vpw, and that of the PFET 202 is set by Vnw. It is noted that in other designs, in which a number of transistors are formed in a common well, the bias potential may be routed within the surface well.
FIG. 2(b) illustrates a similar design, except that the substrate or bulk of the NFET 201 is biased to Vpw by way of a metallic back plane 219, rather than by way of the well tie 216 shown in FIG. 2(a).
Splitting off the well ties as in FIGS. 2(a) and 2(b) is a relatively simple exercise in the case where the configuration is designed into the methodology from the outset. On the other hand, in the case of existing designs not employing back-biasing, since necessary alterations include modifying the surface layout of the design, retrofitting after the fact to allow for splitting off well ties is intensively time-consuming.
This process of modifying the layout to split off the well ties includes first removing the well ties that are connected to the supply rails and then finding some space in the layout to allow for rails to separately carry the substrate potentials. These are serious issues, particularly with respect to large complex layouts having high component densities. Many designs already utilize most, if not all, to available surface area, and the provision of extra metallic rails is a severe design challenge in many instances.
In accordance with one embodiment of the present invention, a semiconductor device is provided which includes a bulk material of a first conductivity having a front side and a back side, wherein the back side of the bulk material is supplied with a first potential; first wells of the first conductivity formed in the front side of the bulk material, wherein at least one of the first wells is supplied with the first potential; second wells of the first conductivity formed in the front side of the bulk material, wherein at least one of the second wells is supplied with a second potential which is different than the first potential; third wells of a second conductivity formed in the front side of the bulk material; and a first buried layer of the second conductivity extending between the back side of the bulk material and the first, second and third wells, the first buried layer having at least one opening therein to electrically connect the bulk material with the at least one of the first wells supplied with the first potential; wherein the at least one of the second wells supplied with the second potential is electrically isolated from the at least one opening of the first buried layer by at least one of the plurality of third wells.